Oversampled continuous-time pipeline ADC with voltage-mode summation
US10171102B1 · kind B1 · utility
6Cited by
29References
25Claims
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Key dates
| Filing date | Jan 9, 2018 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/414
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.