Equalizer circuit and integrated circuit including the same
US10171269B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Apr 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03535
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.