IP route caching with two search stages on prefix length
US10171419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L67/568
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A first determination is made that a number M of the most significant bits of a cache entry and the destination address are identical. A second determination is made that an additional number M+L of the most significant bits of a cache entry and the destination address are identical. Routing information is then retrieved the cache memory, and the packet processed according to the routing information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.