Elimination method of parasitic capacitance and device
US10175812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jan 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure discloses an elimination method of parasitic capacitance and a device. During a touch scanning period, inputting a first simulation signal to source electrode lines and inputting a second simulation signal to multiplex lines can eliminate parasitic capacitance. Waveforms of the first simulation signal and a touch scanning signal input in a common electrode are identical or similar, waveforms of the second simulation signal and the touch scanning signal input in the common electrode are similar, waveforms of the third simulation signal and the touch scanning signal input in the common electrode are similar, a second simulation waveform includes a first target high level, a second target high level, a first target low level and a second target low level that are generated by different modules, the first target high level>the second target high level>the first target low level>the second target low level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.