Patent · US Active

Predictive scheduler for memory rank switching

US10175893B2 · kind B2 · utility

2Cited by

19References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

James J. Bonanno · Wappingers Falls, US
Michael J. Cadigan, Jr. · Poughkeepsie, US
Adam B. Collura · Hopewell Junction, US
Daniel Lipetz · Poughkeepsie, US
Patrick J. Meaney · Poughkeepsie, US
Craig R. Walters · Highland, US

Key dates

Filing date	Jul 26, 2017
Grant date	Jan 8, 2019
Priority date	—
Expiry date	Jul 26, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Scheduling memory accesses in a memory system having a multiple ranks of memory, at most r ranks of which may be powered up concurrently, in which r is less than the number of ranks. If fewer than r ranks are powered up, a subset of requested powered down ranks is powered up, such that at r ranks are powered up, the subset of requested powered down ranks to be powered up including the most frequently accessed requested powered down ranks. Then, if fewer than r ranks are powered up, a subset of unrequested powered down ranks is powered up, such that a total of at most r ranks is powered up concurrently, the subset of unrequested powered down ranks to be powered up including the most frequently accessed unrequested powered down ranks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.