Explicit instruction scheduler state information for a processor
US10175988B2 · kind B2 · utility
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124References
20Claims
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Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Mar 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3854
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method including fetching a group of instructions, where the group of instructions is configured to execute atomically by a processor, is provided. The method further includes scheduling at least one of the group of instructions for execution by the processor before decoding the at least one of the group of instructions based at least on pre-computed ready state information associated with the at least one of the group of instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.