Integration pattern implementations using reconfigurable logic devices

US10176146B2 · kind B2 · utility

Assignee

• SAP SE · DE

Inventors

• Daniel Ritter · Heidelberg, DE
• Jonas Dann · Heidelberg, DE

Key dates

• Filing date: Dec 16, 2016
• Grant date: Jan 8, 2019
• Expiry date: Jun 26, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G05B19/045
• WIPO field: Control
• WIPO sector: Instruments

Abstract

Example embodiments of the present disclosure include an integration system comprising a machine-readable medium (e.g., a memory) and a reconfigurable logic device (e.g., an FPGA). The machine-readable medium stores configuration data that configures the reconfigurable logic device to include a first channel adapter, a first message processor, a second message processor, a message channel, and a second channel adapter. The first channel adapter is configured to receive input data written by a first message endpoint. The first message processor is configured to perform a first message processing operation on messages received from the first channel adapter that include the input data. The second message processor is configured to perform a second message processing operation on messages received from the first message processor. The message channel facilitates communication between the first and second message processors. The second channel adapter is configured to forward output data to a second message endpoint for further processing.