Memory decoding system
US10176854B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2018 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jan 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.