SiC epitaxial wafer and method for manufacturing the same
US10176987B2 · kind B2 · utility
1Cited by
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3Claims
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Key dates
| Filing date | May 4, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | May 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A SiC epitaxial wafer including: a SiC epitaxial layer that is formed on a SiC substrate having an off angle, wherein the surface density of triangular defects, in which a distance from a starting point to an opposite side in a horizontal direction is equal to or greater than (a thickness of the SiC epitaxial layer/tan(x))×90% and equal to or less than (the thickness of the SiC epitaxial layer/tan(x))×110%, in the SiC epitaxial layer is in the range of 0.05 pieces/cm2 to 0.5 pieces/cm2 (where x indicates the off angle).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.