Patent · US Active

Embedded SiGe epitaxy test pad

US10177049B2 · kind B2 · utility

0Cited by

0References

10Claims

0Family size

Assignee

Shanghai Huali Microelectronics Corporation · CN

Inventors

Haifeng Zhou · Singapore, SG
Jun Tan · Shanghai, CN

Key dates

Filing date	Mar 28, 2018
Grant date	Jan 8, 2019
Priority date	—
Expiry date	Mar 28, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/822
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Techniques for measuring and testing a semiconductor wafer during semiconductor device fabrication include designating a test area on the top surface of the wafer and etching a first rectangular trench and a second rectangular trench on the top surface of the wafer in the test area. The trenches are oriented such that a length of the first trench is perpendicular to a length of the second trench, and positioned such that the length of the first trench, if extended, intersects the length of the second trench. A silicon-germanium compound is deposited into the first trench and the second trench, and a test pad is removed from the test area of the wafer. The test pad includes a side surface where both the first trench and the second trench are exposed. The side surface of the test pad is scanned with a transmission electron microscope to take measurements of the silicon-germanium.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.