Tamper-proof electronic packages with stressed glass component substrate(s)
US10177102B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Tamper-proof electronic packages and fabrication methods are provided which include a glass substrate. The glass substrate is stressed glass with a compressively-stressed surface layer. Further, one or more electronic components are secured to the glass substrate within a secure volume of the tamper-proof electronic package. In operation, the glass substrate is configured to fragment with an attempted intrusion event into the electronic package, and the fragmenting of the glass substrate also fragments the electronic component(s) secured to the glass substrate, thereby destroying the electronic component(s). In certain implementations, the glass substrate has undergone ion-exchange processing to provide the stressed glass. Further, the electronic package may include an enclosure, and the glass substrate may be located within the secure volume separate from the enclosure, or alternatively, the enclosure may be a stressed glass enclosure, an inner surface of which is the glass substrate for the electronic component(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.