Semiconductor device and structure
US10177147B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/937
Abstract
A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.