Delay line with short recovery time
US10177751B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00234
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes a plurality of cascaded delay elements responsive to control signals. Each delay element is configurable to receive an input signal on a forward path and return the input signal on two return paths. A control unit is connected to the plurality of cascaded delay elements and configured to generate a first set of control signals for defining a first configuration of the plurality of cascaded delay elements, a second set of control signals for causing a delay element of the plurality of cascaded delay elements to change from a powered off status to a powered on status while configured in an initialization mode, and a third set of control signals for defining a second configuration of the plurality of cascaded delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.