Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation
US10177772B2 · kind B2 · utility
1Cited by
5References
19Claims
0Family size
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Key dates
| Filing date | Sep 21, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Sep 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.