Method and apparatus for conducting automated integrated circuit analysis
US10180402B2 · kind B2 · utility
4Cited by
17References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 29, 2013 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Jul 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for scanning an integrated circuit comprising a plurality of time-synchronized laser microscopes, each of which is configured to scan the same field of view of an integrated circuit under test that generates a plurality of images of the integrated circuit under test, a data processor, coupled to the laser scanning microscope, for processing the plurality of images, comprising, a netlist extractor (NE) that produces one or more netlists defining structure of the integrated circuit under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.