Systems and methods of testing multiple dies
US10180454B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2016 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318511
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing a semiconductor wafer comprising a scribe line and a plurality of dies. The method includes implementing a first landing pad on the scribe line and implementing a first interconnect on the scribe line and between the first landing pad and a first cluster of the plurality of dies, thereby coupling the first landing pad to the first cluster of dies. The method also includes performing the testing of the first cluster of dies using automated test equipment (ATE) coupled to a probe tip by contacting the first landing pad with the probe tip and applying an ATE resource to the first cluster of dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.