Display panel and thin film transistor array substrate
US10180611B2 · kind B2 · utility
1Cited by
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16Claims
0Family size
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Key dates
| Filing date | Aug 13, 2015 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Aug 13, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2203/04103
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A liquid crystal display panel and a thin film transistor array substrate are provided. The thin film transistor array substrate includes a pixel area and a fan-out area. The fan-out area has a groove. The thin film transistor array substrate has a substrate, a light shielding layer, a buffer layer, a poly-silicon layer, a first insulating layer, a scan line layer, a second insulating layer, a data line layer, a third insulating layer, a common line layer, a touch-sensing line layer, a fourth insulating layer, and a pixel electrode layer. The present invention can prevent wire shorts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.