Intelligent memory architecture for increased efficiency
US10180803B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Jul 28, 2015 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0688
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes receiving a first request, from a first master core, to access data in one of a plurality of memory banks. It is determined whether an access to the data is stalled by virtue of a second request, from a second master core, to access the data in the one of the plurality of memory banks, the second request currently being serviced. In response to a determination that the access to the requested data is stalled, the first request is serviced by accessing data in one of a plurality of coding banks, each coding bank smaller in size than each memory bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.