Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer
US10181430B2 · kind B2 · utility
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6References
10Claims
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Key dates
| Filing date | Jun 27, 2014 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Jun 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic hardware assembly including at least a first and second laminar component, wherein the first laminar components includes a die, the die including a substrate, a functional region and a first protective layer, and the second laminar component includes a second protective layer, wherein the first and second laminar components are arranged in a stack such that the functional region of the first laminar component is arranged within the assembly substantially between first and second protective layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.