Methods and apparatus for performing reed-solomon encoding
US10181864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2016 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/617
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.