Gain level control circuit supporting dynamic gain control in a wireless communications system (WCS)
US10181906B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2018 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Mar 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B10/25759
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A gain level control circuit in a wireless distribution system (WDS) is provided. The digital level control circuit receives a number of first digital communications signals having a number of first digital amplitudes and generates a number of second digital communications signals having a number of second digital amplitudes. When a selected second digital amplitude approaches a full-scale digital amplitude represented by a predefined number of binary bits, the gain level control circuit determines a selected first digital communications signal having a selected first digital amplitude causing the selected second digital amplitude to exceed the full-scale digital amplitude and adjusts the selected first digital amplitude to reduce the selected second digital amplitude to lower than or equal to the full-scale digital amplitude. As such, it is possible to overcome digital amplitude clipping without increasing the predefined number of binary bits, thus achieving a calculated balance between performance, complexity, and cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.