Sampling phase adjustment device and adjusting method thereof
US10181941B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | May 18, 2018 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | May 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sampling phase adjustment device and an adjusting method thereof are disclosed. Sampling phase adjustment device includes feedback summer, adaptive equalizer unit, clock and data recovery (CDR) circuit, data slicer, error slicer, sample calculator unit and enable circuit. The adjusting method is as follows: the data slicer and error slicer receive a sum value generated from the feedback summer, and generate a data signal and an error signal, respectively. The adaptive equalizer unit provides an equalizing signal to the feedback summer and a reference signal to the error slicer. The sample calculator unit generates a sampling adjustment signal based on the data signal and error signal. The CDR circuit is configured to output and adjust a clock signal based on the sampling adjustment signal and data signal. The enable circuit enables the adaptive equalizer unit and the sample calculator unit alternatively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.