On-chip optical interconnection structure and network
US10185085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Dec 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/0005
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An on-chip optical interconnection structure and network, where the on-chip optical interconnection structure includes M levels of optical switches, and mth-level optical switches in the M levels of optical switching devices include 2m-1 optical switches. Each optical switch in (i-1)th-level optical switches in the M levels of optical switches is coupled to two optical switches in ith-level optical switches. Two optical switches in the ith-level optical switches coupled to a same optical switch in the (i-1)th-level optical switches are coupled. The on-chip optical interconnection network is divided into levels, and switches coupled in a grid manner are formed such that hierarchical switching may be performed, and conflicts and delays in communication are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.