Methods and apparatus for controlling power consumption of a computing unit that employs a discrete graphics processing unit
US10185386B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus controls power consumption of a computing unit by determining a discrete frame buffer memory usage condition, such as when there is little real 3D activity (or other condition). When the discrete frame buffer memory usage condition is favorable for power savings, the method and apparatus reduces power to at least one bank of discrete frame buffer memory during runtime of an associated discrete graphics processor. The associated discrete graphics processor uses a portion of a system memory's frame buffer memory instead of the at least one bank of discrete frame buffer memory during runtime of the discrete graphics processor. When a user runs more intense 3D programs, the apparatus and method dynamically enables the discrete frame buffer or portion thereof such as one or more banks and reverts from using the system memory back to using the discrete frame buffer memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.