Reading and writing to NAND flash memories using charge constrained codes
US10185623B2 · kind B2 · utility
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10Claims
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Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.