Semiconductor integrated circuit device
US10186504B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.