Configurable delay line
US10187040B2 · kind B2 · utility
0Cited by
3References
21Claims
0Family size
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Inventor
Key dates
| Filing date | Sep 11, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delaying element includes a first XOR logic gate and a second XOR logic gate. A first input of the first XOR logic gate defines an input terminal. A first input of the second XOR logic gate is connected to an output of the first XOR logic gate. An output of the second XOR logic gate defines an output terminal. The second inputs of the first and second XOR logic gates are connected to a second input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.