Scalable architecture for digital signal processing
US10187142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2015 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Sep 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Architecture is described for implementing digital signal processors, defined by a plurality of physically distinct processing modules connected by high speed digital interconnections in which a first plurality of first modules have a plurality of analog or digital signal inputs and arranged to perform a first set of digital processing functions and produce a first plurality of digital interconnection outputs, a second plurality of second modules are arranged to receive the first plurality of digital interconnection outputs and perform a second set of digital processing functions and produce a second plurality of digital interconnection outputs, and a third plurality of third modules are arranged to receive the second plurality of digital interconnection outputs and perform a third set of digital processing functions and produce a plurality of analog or digital signal outputs, wherein the architecture is scalable by selection of the number of first modules, the number of second modules and the number of third modules and the interconnections between them such that the signal processing required of a digital signal processor is achieved through the distribution of the processing ove…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.