Apparatus and method for self-testing an integrated circuit
US10191110B2 · kind B2 · utility
1Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2016 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Apr 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/08
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit and a method of self-testing the integrated circuit are provided. The method comprises: generating a reference voltage at an output of a reference circuit; initiating a test of the reference circuit during a test mode; determining whether the test of the reference circuit passes; and comparing, if the test of the reference circuit passes, a first voltage with the reference voltage. The disclosed test method provides for more complete testing of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.