Time to digital converter and phase locked loop
US10191453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2016 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Dec 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.