Versatile packed data comparison processors, methods, systems, and instructions
US10191743B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2013 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including a decode unit to decode a versatile packed data compare instruction to indicate a first source packed data operand to include a first plurality of data elements, a second source packed data operand to include a second plurality of corresponding data elements. The instruction to indicate a source comparison operation indication operand to include comparison operation indicators each to indicate a potentially different comparison operation for a different corresponding pair of data elements from the first and second source operands. An execution unit, in response to the instruction, to store a result in a destination storage location indicated by the instruction. Result to include result indicators each to correspond to a different one of the comparison operation indicators. Each result indicator to indicate a result of a comparison operation, indicated by the corresponding comparison operation indicator, performed on the corresponding pair of data elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.