Scatter reduction instruction
US10191749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Apr 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.