Method to efficiently trigger concurrency bugs based on expected frequencies of execution interleavings
US10191833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes determining a set of shared memory access instructions and execution frequencies and selecting one or more groups of instructions that access a same memory location. The method also includes finding pairs of instructions from each group, for which another access to the same memory location may occur between execution of the instructions in the pair, and estimating a probability that a data race may occur using a time gap between the instructions and the execution frequencies, and generating a list of instruction tuples that include the pair of instructions. The method includes calculating a score for each instruction in the tuples, the score representing a likelihood of triggering a data race by injecting a delay before an instruction. The method includes selecting instructions having a score indicating a lower than a threshold probability that the instruction will comprise a last access of a data race.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.