Method and system for aggregation-friendly address assignment to PCIe devices
US10191882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Feb 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.