Patent · US Active

Generating and inserting metal and metal etch shapes in a layout to correct design rule errors

US10192021B1 · kind B1 · utility

11Cited by

25References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Satish Raj · Saratoga, US
Ying Wang · San Jose, US
Joyjeet Bose · Noida, IN
Sachin Shrivastava · Noida, IN

Key dates

Filing date	Feb 21, 2017
Grant date	Jan 29, 2019
Priority date	—
Expiry date	Mar 6, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.