Low cost inbuilt deterministic tester for SOC testing
US10192633B2 · kind B2 · utility
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5References
14Claims
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Key dates
| Filing date | Mar 1, 2016 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Mar 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.