Thin film transistor and method of manufacturing the same, array substrate and display panel
US10192894B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | May 2, 2016 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Feb 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
Embodiments of the present application provide a thin film transistor and a method of manufacturing the same, an array substrate and a display panel. The thin film transistor comprises, successively from the bottom up, a gate, a first common electrode located in the same layer as the gate, a gate insulating layer, an active layer, a pixel electrode, a source-drain electrode layer and a passivation layer located above the layer where the gate is located, and a second common electrode located on the passivation layer, and the thin film transistor further comprises at least one connection electrode located in a same layer as the pixel electrode, wherein at least two via holes are provided between the first common electrode and the second common electrode so as to connect the first common electrode and the second common electrode through the connection electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.