Flat STI surface for gate oxide uniformity in Fin FET devices
US10192988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jul 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.