Digital phase locked loop circuit adjusting digital gain to maintain loop bandwidth uniformly
US10193562B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Nov 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop circuit includes a phase frequency detector, a bandwidth calibrator, a digital loop filter, and a digital controlled oscillator. The phase frequency detector generates a first detection value and a second detection value of which each is associated with order between a phase of a reference signal and a phase of a fed-back signal. The bandwidth calibrator amplifies a signal level of the second detection value by a gain value to generate an amplified detection value, and adjusts the gain value based on the first detection value. The digital loop filter generates a digital code based on the amplified detection value. The digital controlled oscillator generates an output signal having a frequency which corresponds to the digital code. The fed-back signal is generated based on the output signal and is fed back to the phase frequency detector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.