Array substrate and method for manufacturing the same and display device
US10197877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Sep 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136254
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate includes multiple pattern layers disposed in a display region and a test unit disposed in a non-display region, the test unit includes at least one of a test component and a test transistor. The test component includes a test block pattern and a test line pattern; the test block pattern is disposed in the same layer as one layer of the multiple pattern layers, the test line pattern is disposed in the same layer as one layer of the multiple pattern layers, and the test block pattern and the test line pattern are disposed in different layers; the orthographic projection of the test line pattern on the array substrate surrounds the periphery of the orthographic projection of the test block pattern on the array substrate; and the test block pattern or the test line pattern is connected to the test transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.