Glitch-free clock multiplexer
US10198026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Apr 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system having a first clock domain with a first clock and a second clock domain with a second clock, the first and second clocks are monitored to determine whether one or both clocks are active. The first clock is selected to be an output clock if the first clock is active and the second clock is disabled irrespective of the clock selection signal. The second clock is selected to be the output clock if the second clock is active and the first clock is disabled irrespective of the clock selection signal. If both the first clock and the second clock are active, either the first clock or the second clock is selected according to a received clock selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.