Data processing
US10198268B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Oct 11, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing element comprises a plurality of function units (16) operable to execute respective functions in dependence upon received instructions in parallel with one another. An instruction controller includes an instruction register (41) having a plurality of register entries, each of which is operable to store an instruction word therein, and a plurality of instruction pipelines (42). Each of the pipelines (42) is associated with a function unit (16), and is operable to deliver instructions to the function unit concerned for execution thereby. Each pipeline also includes a timing controller operable to receive timing information for a received instruction, and to determine an initial location in the pipeline into which the instruction is to be loaded, and an instruction handler operable to receive an instruction for the function unit associated with the instruction pipeline concerned, and to load that instruction into the initial location determined by the timing controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.