Providing error correcting code (ECC) capability for memory
US10198310B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Nov 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes, in at least one aspect, designating a first region of a memory device for storing data of a first type and first error correcting code (ECC) data; designating a second region for storing data of a second type and second ECC data; receiving the data of the first type; generating the first ECC data for the data of the first type using a first ECC associated with a first ECC protection level; storing the data of the first type and the first ECC data in adjacent locations of the first region; receiving the data of the second type; generating the second ECC data for the data of the second type using a second ECC associated with a second ECC protection level; and storing the data of the second type and the second ECC data in the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.