Systems and methods for addressing a cache with split-indexes
US10198359B2 · kind B2 · utility
1Cited by
2References
27Claims
0Family size
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Key dates
| Filing date | Feb 23, 2018 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/455
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.