Configurable on-chip interconnection system and method and apparatus for implementing same, and storage medium
US10198374B2 · kind B2 · utility
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Key dates
| Filing date | Apr 15, 2015 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Apr 15, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing a configurable on-chip interconnection system. The method comprises: in an interconnection system, master devices set bit widths of bus identifiers of the master devices, wherein the bit widths of the bus identifiers of the master devices are the same (301); and in a memory access process, the mater devices interact, by means of interconnection matrices only, with slave devices according to the bus identifiers (302). Also provided are a system and apparatus for implementing the method, and a storage medium.
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