Max pooling in a matrix processing architecture
US10198401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Feb 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix operation comprises a max pooling operation on one or more matrix operands. The plurality of processing elements comprises one or more matrix processors, and the plurality of processing elements is configured to: receive matrix data from the multi-dimensional memory, wherein the matrix data is associated with the one or more matrix operands; extract the one or more matrix operands from the matrix data; perform the max pooling operation using the one or more matrix operands; and obtain a result of the max pooling operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.