Write operation scheme for SRAM
US10199094B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.