Semiconductor structure and fabrication method thereof
US10199297B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 30, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Nov 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and fabrication methods thereof are provided. An exemplary semiconductor structure includes a semiconductor substrate having a device region and a protective region around the device region; a seal ring structure on the semiconductor substrate in the protective region; an electrical interconnect structure on the semiconductor substrate in the device region; an interlayer dielectric layer entirely covering the protective region on the seal ring structure and the electrical interconnect structure; a solder pad electrically connected with the electrical interconnect structure passing through a portion of the interlayer dielectric layer in the device region; a passivation layer on the interlayer dielectric layer and exposing the solder pad; and a conducive wire connected to the solder pad and across over a portion of the passivation layer in the protective region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.