Methods of manufacturing semiconductor packages
US10199366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jul 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package, the method including forming a hole that penetrates an interconnect substrate; providing a first carrier substrate below the interconnect substrate; providing a semiconductor chip in the hole; forming a molding layer by coating a molding composition on the semiconductor chip and the interconnect substrate; adhering a second carrier substrate onto the molding layer with an adhesive layer; removing the first carrier substrate to expose a bottom surface of the semiconductor chip and a bottom surface of the interconnect substrate; forming a redistribution substrate below the semiconductor chip and the interconnect substrate; detaching the second carrier substrate from the adhesive layer; and removing the adhesive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.