Nonvolatile memory device and method of manufacturing the same
US10199390B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jul 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/667
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.